1. Field of the Invention
The present invention relates to a capacitor component and a method of producing the same, and in particular, to a capacitor component where an electrostatic capacitance portion includes a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated, and a method of producing the capacitor component.
2. Description of the Related Art
In general, a multilayer ceramic capacitor as a capacitor component includes an element assembly formed by a plurality of dielectric layers made of a ceramic material and a plurality of internal electrode layers made of a conductive material being alternately laminated, and an electrostatic capacitance portion is formed by the laminated plurality of dielectric layers and the laminated plurality of internal electrode layers.
Usually, each of a pair of internal electrode layers positioned across the dielectric layer is extended toward a mutually different direction, and thereby being directly extended to a mutually different end surface of the element assembly. Each of a pair of external electrodes is provided so as to cover the corresponding one of a pair of end surfaces of the element assembly and is connected to the corresponding one of the pair of internal electrode layers.
In this kind of multilayer ceramic capacitor, the increase in capacity can be relatively easily achieved by increasing the number of laminated layers of the dielectric layers and the internal electrode layers, but on the other hand, the equivalent series resistance (ESR) is lowered. This is caused by the total cross-sectional area of the conductive path being relatively increased with the increase of the number of laminated layers of the internal electrode layers.
Therefore, when the multilayer ceramic capacitor is used for decoupling applications, various problems due to the low ESR (for example, the increase in impedance due to the anti-resonance with another capacitor component, the oscillation of the DC-DC converter, the ringing during the transient response, and the like) may occur.
A technology to achieve a higher ESR in this type of multilayer ceramic capacitor is, for example, disclosed in JP 2010-103184 A. In the multilayer ceramic capacitor disclosed in JP 2010-103184 A, all of a plurality of internal electrode layers to be electrically connected to a first external electrode are connected by being drawn to a first side surface of the element assembly with terminal conductors provided on the first side surface interposed therebetween, and only a portion of the plurality of internal electrode layers are connected to the first external electrode by being drawn to the first end surface of the element assembly, and all of a plurality of internal electrode layers to be electrically connected to a second external electrode are connected by being drawn to a second side surface of the element assembly with terminal conductors provided on the second side surface interposed therebetween, and only a portion of the plurality of internal electrode layers are connected to the second external electrode by being drawn to the second end surface of the element assembly.
By using the multilayer ceramic capacitor disclosed in JP 2010-103184 A, compared to the case where all of the internal electrode layers are configured to be directly extended to the end surface of the element assembly, the total cross-sectional area of the conductive path can be reduced, and therefore, a higher ESR can be achieved.
However, when the multilayer ceramic capacitor disclosed in JP 2010-103184 A is used, a problem that a major limitation arises occurs with respect to the mounting on the wiring board.
That is, in the multilayer ceramic capacitor disclosed in JP 2010-103184 A, when the pair of terminal conductors are directly connected to the conductive patterns and lands provided on the wiring board with solder bonding material and the like interposed therebetween, the effect itself of the above described higher ESR is eliminated. Therefore, in the multilayer ceramic capacitor, a sufficient margin is necessary to be previously provided on the wiring board so that the pair of terminal conductors are not directly connected to the conductive patterns and lands even after the mounting to the wiring board.
Therefore, a design of a wiring board different from the wiring board corresponding to the conventional general multilayer ceramic capacitor is required.
In other words, as described above, the multilayer ceramic capacitor disclosed in JP 2010-103184 A requires a sufficient margin to be previously provided on the wiring board so that the pair of terminal conductors are not directly connected to the conductive patterns and lands on the wiring board even after the mounting to the wiring board, and as a result, requires an extra mounting space, and therefore, the high density mounting is hindered.
In addition, the multilayer ceramic capacitor disclosed in JP 2010-103184 A is in a state where not only a pair of external electrodes are exposed, but even the pair of terminal conductors are exposed on the surface of the element assembly, and therefore, the surface area of the element assembly has to be sufficiently secured so that the mutual short circuit between the pair of external electrodes and the pair of terminal conductors is prevented. Therefore, the multilayer ceramic capacitor has a difficulty in implementing even the miniaturization of itself, and the high density mounting is hindered also in this regard.